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M65677FP
Digital NTSC/PAL Encoder
REJ03F0189-0201 Rev.2.01 Mar 31, 2008
Description
The M65677FP encodes CCIR601 or CCIR656 format Y/Cb/Cr data into analog NTSC and PAL video signals, including Digital Signal Processing functions such as Closed Caption encoding. Overlay OSD, Anti Video Copy Processing Note1 e.t.c. It also includes peripheral processing function such as 10 bit DAC e.t.c., so that low cost and compact system can be realized.
Features
* * * * * * * * * * * * * * * * * Macrovision's video anti copy process Rev 7.01 supported Note1 Overlay CGMS signal online 20/283 for 525/60 Note3 Generate CRCC for CGMS Signal Overlay WSS signal online 23 for 625/50 Note4 Color adjustment (TINT/color control) NTSC, B/G PAL or MPAL Video Outputs Component Y/C Video (S-Video) and CVBS or Y/U/V Outputs Supporting CCIR601 and CCIR656 format data Closed Caption Manager online 21/284 for NTSC Generate ODD parity for Closed Caption Manager H/V Sync and Composite generating Overlay Digital OSD Supporting Y/Cb/Cr 4:4:4 Over sampling Filter 2 ch 10 bit DAC and 3 ch 6 dB Amp Note2 3.3 V I/O interface I2C Bus Interface for Controls Power down mode Notes: 1. This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. The use of Macrovision Corporation's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-par-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. 2. 6 dB Amp max. output is 1.0 Vp-p 3. Copy Generation Management System-A (IEC1880) 4. Wide Screen Signaling (ETS300 294)
Application
DVB, DVD, Digital CATV, Video CD
REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 1 of 8
M65677FP
Block Diagram
OSD control I/F AVDD1 Y ref C ref
LPF
OSD2 OSD1 OSD0
AVSS1
BPF
DAY
OSDCK
AVSS2
AVDD2
Cin Yin
DAC
REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 2 of 8
Y
Closed caption manager
Y Cb Y/Cb/Cr U Cr
Encode Y/U/V CGMS/WSS manager
Y Y/U DAC
Clamp & bias
6 dB
PXD [7:0]
Y
Cb
OSD interface
Y Cr C/V V
Input interface
6 dB
C DAC
CCIR601 or 656 pixel data from MPEG decoder
Anti copy processing SYNC processing Serial interface
Video output
VD [9:0]
Y/C MIX
6 dB
CVBS
HD
TEST RESET
From/to MPEG decoder
VD
Muster/ slave
ACK
SDA
From micro controller
SCL
DVDD2 (x 2) DVDD1 (x 2) DVSS2 (x 2) DVSS1 (x 2)
M65677FP
Pin Arrangement
M65677FP
Y AVSS2 CVBS N.C. C
37 36 35 34 33
48
47
46
45
Yref Cref DAY AVSS1 AVDD1
43
42
41
40
39
38
44
DAC Ccomp C in N.C. Y in AVDD2
Ycomp N.C. DVDD1 DVSS1 X out X in DVSS2 PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0 DVDD2
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
10 12 13 14 15 16 11 1 2 3 4 5 6 7 8 9
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
N.C. N.C. DVDD1 TEST SCL SDA ACK RESET Master/slave OSD2 OSD1 OSD0 OSDCK DVSS1 DVDD1 DVDD2
DVSS2
PXCLK DVASEL
HD VD VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 DVSS2
NC: No connection
(Top view) Outline: PRQP0064GA-A (64P6N-A)
REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 3 of 8
M65677FP
Pin Description
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name DVSS2 PXCLK DVASEL HD VD VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 DVSS2 DVDD2 DVDD1 DVSS1 OSDCK OSD0 OSD1 OSD2 Master/Slave Type Supply O I I/O I/O I/O Function Digital ground for the I/O Reference clock for input pixel data. The clock frequency is 27.0 MHz I2C slave address setting. "Low" is for the address of 40h, "High" is for the address of 42h. Horizontal sync signal input or output. It is an input and output in the slave and master mode, respectively. Vertical sync input or output. Or Odd Even signal output. It is an input and output in the slave and master mode, respectively. Video data outputs. In the Y/U/V output mode, the output is the 10-bit digital luma signal with a composite sync. VD9 is MSB and VD0 is LSB.
Supply Supply Supply Supply O I
Digital ground for the I/O. Digital supply for the I/O Digital supply for the internal logic. Digital ground for the internal logic. The reference clock for an external OSD microcontroller. 2 The frequency is 13.5 MHz or 6.25 MHz, alternated by I C bus control. The color look-up table address input. MSB and LSB are OSD2 and OSD0, respectively. Synchronizing mode selection. "Low" is for the slave mode. "High" is for the master mode. Initializing reset. "Low" is active. Acknowledge line (Open drain output). Serial data line/acknowledge line (Open drain output). Serial clock line. For testing. Is should be grounded during an actual use. Digital supply for the internal logic. No connection. No connection. The analog chroma output from a 6 dB amplifier. The output amplitude is 1.0 VP-P (Typ), while the input is 0.5 VP-P. No connection. The analog composite video signal from a 6 dB amplifier. The output amplitude is 1.24 VP-P (Typ). Analog ground for 6 dB amplifiers. The analog luma output from a 6 dB amplifier. The output amplitude is 1.2 VP-P (Typ), while input is 0.6 VP-P. Analog supply for 6 dB amplifiers.
I
25 26 27 28 29 30 31 32 33 34 35 36 37 38
RESET ACK SDA SCL TEST DVDD1 N.C. N.C. C N.C. CVBS AVSS2 Y AVSS2
I O I/O I I Supply -- -- O -- O Supply O Supply
REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 4 of 8
M65677FP
Pin Description (cont.)
Pin No 39 40 41 42 43 Pin Name Yin N.C. Cin Ccomp DAC Type I -- I I O Function The analog luma input from an external LPF. This input has bias circuit. The signal must input via a capacitor. No connection. The analog chroma input from an external LPF. This input has bias circuit. The signal must input via a capacitor. Phase compensation for chroma or V output DAC. It should be connected to the analog ground via a capacitor. Chroma or V signal output. The DAC output should be connected to the analog supply via a load resistor (RL). The output amplitude is set up by reference resistor (Rref) and RL. Analog supply for DACs. Analog ground for DACs. Luma or U signal output. It should be connected to the analog supply via a load resistor (RL). The output amplitude is set up by reference resistor (Rref) and RL. A reference current source for chroma or V signal output DAC. It should be connected to the analog supply via a reference resistor (Rref). A reference current source for Y or U DAC. It should be connected to the analog supply via a reference resistor (Rref). Phase compensation for Y or U DAC. It should be connected to the analog ground via a capacitor. No connection. Digital supply for the internal logic. Digital ground for the internal logic. System clock output. It must be in no connection except for a connection to a Xtal oscillator. System clock input. The clock frequency is only 27.0 MHz. Digital ground for the I/O. Pixel data inputs. The acceptable video data are; * Multiplexed video data (Y/Cb/Cr) including timing reference code of SAV and EAV, defined in CCIR Rec656 * Multiplexed video data (Y/Cb/Cr) defined in CCIR Rec601 MSB and LSB are PXD7 and PXD0, respectively.
44 45 46
AVDD1 AVSS1 DAY
Supply Supply O
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Cref Yrel Ycomp N.C. DVDD1 DVSS1 Xout Xin DVSS2 PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0 DVDD2
I I I -- Supply Supply O I Supply I
Supply
Digital supply for the I/O.
Absolute Maximum Ratings
Item Supply voltage Digital input voltage Digital output voltage Operating temperature Storage temperature Symbol VDD VI VO Ta Tstg Min -0.3 -0.3 -0.3 -20 -40 Limits Typ -- -- -- +25 -- Max 4.5 VDD + 0.3 VDD + 0.3 +75 +125 Unit V V V C C
REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 5 of 8
M65677FP
Recommended Operating Condition
(Ta = 25C, DVDD = AVDD = 3.3 V, DVSS = AVSS = 0 V, unless otherwise noted)
Item Supply Digital supply voltage Analog supply voltage Digital current consumption Analog current consumption Digital input Input voltage Input leakage current Input capacitance Digital output Output voltage Output capacitance I2C Bus Output current Output leakage current (off) D/A converter Resolution Integral non-linearity error Differential non-linearity error Maximum output amplitude 6-dB amplifier Bias resistor Output gain (Y/C) Output Gain (CVBS) Input dynamic range Output dynamic range Yin clamp charge current Yin clamp discharge current Yin clamp discharge current Yin input clamp voltage Yin output clamp voltage CVBS output clamp voltage Cin input bias voltage C output bias voltage Output current Symbol DVDDX AVDDX DIDD AIDD VIL VIH IIL/IIH CI VOL VOH CO IO IOZ Min 3.0 3.15 0 0 0 2.5 -- -- -- 3.25 -- 4.0 -- Limits Typ 3.3 3.3 -- -- -- -- -- 7 -- -- 7 -- -- Max 3.6 3.45 45 55 0.8 3.6 15 15 0.05 -- 15 -- 15 Unit V V mA mA V V A pF V V pF mA A DVDD = 3.0 V DVDD = 3.6 V DVDD = 3.0 V, VI = 0 V or VI = 3.6 V f = 1 MHz, VDD = 0 V DVDD = 3.3 V, |IO| < 1 A f = 1 MHz, VDD = 0 V DVDD = 3.0 V, VIL = 0.4 V DVDD = 3.6 V, VI = 0 V or VI = 3.6 V Test Conditions
Res INL DNL VfsMAX Rbias GV_YC GV_CV DRin DRout Iyich Iyids Ryicl Vyicl Vyocl Vcvcl Vcin Vcob Iamp
-- -- -- 1.5 7.5 5.50 5.10 0.8 1.6 -12 0.26 20 0.45 0.40 0.30 0.95 0.90 1.00
10 -- -- -- 10.0 6.00 6.00 -- -- -26 0.65 0.65 0.50 0.50 0.50 1.00 1.00 --
-- 2.0 1.0 -- 11.5 6.50 6.85 -- -- -50 1.80 70 0.55 0.60 0.70 1.05 1.10 --
Bit LSB LSB Vp-p k dB dB Vp-p Vp-p A A -- V V V V V mA
Iyich Ryicl = - Iyids
REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 6 of 8
M65677FP
Application Example
(CCIR656 I/F, Y/C/CVBS Output Mode)
CVBS
220 F
75
220 F 75 2.2 F
75 Driver
10 k 10 k
0.1 F
2.2 F
Cref
AVDD AVSS Ccomp Ycomp
C CVBS
DAY
Yref
DAC
C in
Y in
47 F 0.01 F
3.3 k
Y
+
TEST Master/slave DVASEL DVSS
0.01 F 47 F
DVDD X out X in
Digital NTSC/PAL encoder M65677FP
PXD (7:0)
OSDCK ACK SDA SCL
3
OSD (2:0)
R/G/B OSC1
Lch
VD (9:0)
PXCLK
27 MHz
VD HD RESET CS SCK SIN
HD VD
Audio DAC
DIN LRCIN BCKIN XTI
0.01 F
47 F
PXCLK
8
VSS + VDD
HSYNC
VSYNC
PXD
SCL SDA/ACK RESET AO 0 AO 1 AO 2 AO 3 LRCLK DOCLK DACCLK
27 MHz XO
CLK in
MPEG2 System/ Video/Audio decoder M65773FP
16 M SDRAM
BCLK BDEN BDREQ
BDER
ACLKO ACLKI
BD
8
3.3 k
RCLK BDEN BDREQ
Channel decoder
: 3.3 V Power supply for analog/digital
REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 7 of 8
RESET CS SCK SIN
BDER
BD
Host CPU
Rch
OSD micro computer M35041
VDD
VSS
RESET
Audio out (R)
Audio out (L)
+
47 F 0.01 F
200
200
0.1 F
0.1 F
+
0.1 F 2.2 F
+
+
Filter stage
Filter stage
0.1 F 75
C
Y
+ +
+
M65677FP
Package Dimensions
JEITA Package Code P-QFP64-14x14-0.80 RENESAS Code PRQP0064GA-A Previous Code 64P6N-A MASS[Typ.] 1.1g
HD *1 D 33
48
49
32
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
17
ZE
64
Reference Symbol
Dimension in Millimeters
1 ZD
16 Index mark F
c
L Detail F
D E A2 HD HE A A1 bp c e y ZD ZE L
e
y
*3 b p
Min Nom Max 13.8 14.0 14.2 13.8 14.0 14.2 2.8 16.5 16.8 17.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.3 0.35 0.45 0.13 0.15 0.2 0 10 0.65 0.8 0.95 0.10 1.0 1.0 0.4 0.6 0.8
REJ03F0189-0201 Rev.2.01 Mar 31, 2008 Page 8 of 8
A1
A
A2
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